 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ASM6312C DATA SHEET ASM6312C ASM6312C - VERY LOW-COST VOICE SYNTHESIZER WITH 4-BIT MICROPROCESSOR 1.0 General Description The ASM6312C is very low cost voice synthesizer with 4-bit microprocessor. It has various features including 4-bit ALU, ROM, RAM, I/O ports, timers, clock generator, watchdog timer(WDT), voice synthesizer, etc. It consists of 22 instructions in the device. With CMOS technology and halt function can minimize power dissipation. Its architecture is similar to RISC, with two stages of instruction pipeline. It allows all instructions to be executed in a single cycle, except for program branches and data table read instructions (which need two instruction cycles). 1.1 Feature Single power supply can operate from 2.4V through 5V Internal Program ROM: 4K x 10-bit 1 sets of 18-bit DPR can access up to 192K x 10 bits data memory space Data Registers: * 96 x 4-bit data RAM (00-1Fh plus 40h-7Fh) * Unbanked special function registers (SFR) range: 20h-3Fh I/O Ports: * PRA: 4-bit I/O Port A (2Bh) * PRB: 4-bit Output Port B (2Dh) * PRC: 4-bit Input Port C (2Fh) On-chip clock generator: Resistive Clock Drive(RM) Timer: 1 * Timer0: a 9-bit auto-reload timer/counter Stack: 2-level subroutine nesting HALT and Release from HALT function to reduce power consumption Watch Dog Timer (WDT) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles Number of instruction: 22 1 Rev 1.0 ASM6312C FIGURE 1.1 : Block Diagram of ASM6312C Data Bus[3:0] ROM Latch PCL(4) PC[11:0] (ADDR[17:12]) =000000b ADDR[17:0] Stack(12) (2-Level) 0 ROM _ADDR[17:0] 1 DPR3,2,1 DPR[17:0] Program (Data) ROM Instruction Latch Instruction Bus [9:0] Instruction Decoder Control Signal DLATCH(10) ROM _Data[9:0] PCLATCH(8) PCH(8) Data Bus[3:0] Accumlator(4) Instruction Bus [9:0] SRAM ALU(4) Register(4) Immediate(4) (96 x 4) 00h-1Fh 40h-7Fh Timer0(9) PRA(4) PRB(4) PRC(4) P1,P2,P3,P4 enter test mode ( Voice synthesizer ) Clock Generator Test select Power on Reset RESET p in PRA0 OSC VDD/GND weak or strong p ull-low for PRA, PRB, PRC PRASL(4) One-Channel Reset Chip Reset Chip COUT COUT 2 Rev 1.0 Instruction Bus [9:0] ASM6312C FIGURE 1.2 : External ROM Map of ASM6312C PC[11:0] 12bit x 2 STACK 18-bit Data Pointer Reset Vector 00000h 00080h Reserved for Testing Program and data ROM 00080h-003FFh 00400h 00000h-00FFFh 00000h-2FFFFh 00FFFh(4K) Data ROM 2FFFFh(192Kx10-bits) 3 Rev 1.0 ASM6312C 1.2 Pin-Out ASM6312C Pin-Out PRC1 PRC0/RESET PRA3-1 PRA0/RESET I I I/O I/O STI Std./O.D. STI Std./O.D. STI Std./O.D. STI Std./O.D. Std./O.D. STI Std./O.D. Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Mask option selected as an external RESET pin with weak pull-low capability I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output I/O port with programmable strong pull-low or weak pull-low or fix-inputfloating capability Output type with standard or Open-Drain output Mask option selected as an external RESET pin with weak pull-low capability RM mode Oscillator input First Power supply during operation Current Output of Audio First Circuit Ground Potential Second Circuit Ground Potential Enter Test Mode. ( TEST = High ) Second Power supply during operation Output type with standard or Open-Drain output Input port with programmable strong pull-low or weak pull-low or fix-inputfloating capability OSC VDD1 COUT GND1 GND2 TEST VDD2 PRB0-3 PRC2-3 I I O I I O I O I 1.3 Application circuit 4 Rev 1.0 ASM6312C 1.4 Bonding Diagram 19 RC3 18 RC2 17 RC1 16 RC0 15 GND2 14 13 12 AOSC VDD2 TEST ( 192K x 10-bit ) Block ROM ASM6312C RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 RB3 1 2 3 4 5 6 7 8 9 10 11 ASM6312C Pad Location PAD # 1 2 3 4 5 6 7 8 9 10 PAD Name RA3 RA2 RA1 RA0 VDD1 COUT GND1 RB0 RB1 RB2 X -682.16 -559.84 -437.52 -315.2 -191.28 71.12 189.52 307.92 430.32 552.56 Chip Size: X=1540+100 (um), Y=2850+100 (um) PAD # PAD Name X Y -1307.72 11 RB3 667.68 -1307.72 -1307.72 12 AOSC 633.56 1339.04 -1307.72 13 TEST 432.48 1339.04 -1307.72 14 VDD2 273.16 1339.04 15 GND2 -1307.72 134.68 1339.04 -1307.72 16 RC0 -51.76 1339.04 -1307.72 17 RC1 -248.4 1339.04 18 RC2 -1307.72 -454.24 1339.04 -1307.72 19 RC3 -650.88 1339.04 Y -1307.72 5 Rev 1.0 ASM6312C 1.5 DC Characteristics for ASM6312C SYMBOL VDD Isb Iop PARAMETER OPERATING VOLTAGE SUPPLY CURREN T STANDBY OPERATING VDD MIN. TYP. MAX. UNIT 2.4 3 5 3 5 3 5 5 3 5 3 5 -10 -20 3 5 1 1 2 7 3 9 -5.2 -3 -8 7 20 10 20 V uA mA CONDITION depending on Freq. 4MHz, RM in HALT Mode 4MHz, RM IO Floating 4MHz, RM in HALT Mode (IO Ports with weak pull-high pull-low) 4MHz, RM (IO ports) Fosc(3v)Fosc(2.4v) Fosc (3v) VDD=3V, Rosc=220k, 4MHz Iih INPUT CURRENT /Internal pull low OUTPUT HIGH CURRENT OUTPUT LOW CURRENT FREQUENCY STABILITY Fosc VARIATION uA Ioh Iol dF/F dF/F mA % % FIGURE 1.3 : Frequency Range for Rosc in RM mode Resistor(k ohm) 3v Freq.(MHz) 330 2.63 220 3.91 Rosc & Freq. 200 4.43 150 5.93 8 Freq. MHz 6 4 2 0 0 100 200 Rosc k ohm 300 400 5.93 4.43 3.91 2.63 6 Rev 1.0 |
Price & Availability of ASM6312C
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |